Highly anticipated: While there’s a Zen Three announcement inbound, we’re getting a variety of key particulars ahead of the October announcement due to leaked developer paperwork. While this leak doesn’t paint the complete picture for what Zen Three goes to seem like, it suggests it must be one different strong CPU assortment for AMD with quite a lot of generational enhancements.
Allegedly confidential paperwork have been leaked by Twitter client CyberPunkCat that seem to provide particulars on modifications to Zen Three that may embody the Ryzen 4000 desktop assortment, code named “Vermeer.”
We know that AMD is taking the wraps off of Zen Three in October, and the small print found inside the paperwork reiterate some points we already know, whereas offering bits of newest information. The doc appears to be a Processor Programming Reference (PPR) for AMD’s Family 19h, Model 21h B0, which may be Zen 3. Previous Zen+ and Zen 2 architectures belong to AMD’s Family 17h, with quite a few fashions and revisions.
AMD typically makes this type of documentation accessible to builders after launch, so it’s not exactly privileged information. Furthermore, this type of developer paperwork are often merely circulated — merely ask Intel.
The most notable modifications to Zen Three look like occurring inside the CCD/CCX configuration. Zen Three will proceed to make the most of a MCM (multi-chip module), or chiplet design, that may use two CCDs and one I/O die. There will solely be one CCX per CCD, and this CCX will embody eight cores capable of working in each single-thread mode (1T) or two-thread SMT mode (2T). So, that’s 16 entire threads per CCX.
This may counsel that Zen Three components will excessive out at 16 cores, within the equivalent pattern as a result of the Ryzen 9 3950X. Though, we’ll must attend and see as AMD may properly have some suggestions up its sleeve.
Furthermore, AMD is reworking its cache subsystem. There may be a whole of 32MB of L3 cache (versus 16MB per CCX with Zen 2) shared all through all eight cores inside the CCX. While Zen 2 offered 32MB of L3 cache per CCD, it wanted to be shared between two separate complexes. There’s moreover 512KB of L2 cache per core all through the CCX, for an entire of 4MB of L2 cache per CCD.
Interestingly, AMD will also be beefing up the Scalable Data Fabric (SDF), which is the communication backbone of Infinity Fabric answerable for the transport of information and coherency between cores, memory controllers, and totally different I/O elements. The paperwork discover that the SDF can now take care of 512GB per DRAM channel. It seems to be like like there could also be some minor modifications to the Scalable Control Fabric (SCF), which is the other half of the Infinity Fabric that primarily handles signaling.
Elsewhere, Zen Three seems to be wish to be bulking up the memory interface with two unified memory controllers (UMC), with each supporting one DRAM channel and each channel supporting two DIMMs. There could even be assist for DDR4-3200, which was natively supported with Zen 2. It seems to be like like Zen Three will principally retain the equivalent choices and connectivity for the Fusion Controller Hub (FCH) that had been present in Zen 2.
In addition to some generational clock velocity bumps, it seems to be like like Zen Three will further polish AMD’s MCM technique, specializing in bettering coherence and latency beneath the hood. We completely depend on a measurable IPC enchancment over Zen 2 components as properly.