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Applied Materials said it has reached a breakthrough in chip wiring that will enable semiconductor chip production to miniaturize to chips so that the width between circuits can be as little as three billionths of a meter.
These so-called 3-nanometer production lines will be part of factories that cost more than $22 billion to build — and generate a lot more revenue than that. The breakthrough in chip wiring will enable logic chips to scale to three nanometers and beyond, the company said.
Big chip manufacturing companies can use the wiring tools in their huge factories, and the transition from 5nm factories to 3nm factories could help ease the shortage of semiconductor chips that has plagued the entire electronics industry. But it will be a while before the chips go into production. In addition to interconnect scaling challenges, there are other issues related to the transistor (extending the use of FinFET transistors and transitioning to Gate All Around transistors), as well as issues related to patterning (extreme ultraviolet and multi-patterning will also have at 3nm).
Santa Clara, California-based Applied Materials is the largest maker of equipment used in semiconductor factories, and so it’s breakthrough will be good for the overall semiconductor industry.
While size reduction benefits transistor performance (smaller chips means that electrons have shorter distances to travel and so computing tasks can be handled faster), the opposite is true in the interconnect wiring: smaller wires
have greater electrical resistance which reduces performance and increases power consumption. Without a materials engineering breakthrough, interconnect via resistance would increase by a factor of 10 from the 7nm node to the 3nm node, negating the benefits of transistor scaling. Current chip factories are making 7nm and 5nm chips. The 3nm chips will represent the next generation of technology.
Applied Materials has developed a new materials engineering solution called the Endura Copper Barrier Seed IMS. It is an Integrated Materials Solution that combines seven different process technologies in one system under high vacuum: ALD, PVD, CVD, copper reflow, surface treatment, interface engineering and metrology. The combination of all of these processes replaces conformal ALD with selective ALD, eliminating a high-resistivity barrier at the via interface.
The solution also includes copper reflow technology that enables void free gap fill in narrow features. Electrical resistance at the via contact interface is reduced by up to 50 percent, improving chip performance and power consumption, and enabling logic scaling to continue to 3nm and beyond. All of this means that the solution improves the flow of electricity through a chip and enables it to operate at the next level of miniaturization.
“A smartphone chip has tens of billions of copper interconnects, and wiring already consumes a third of the chip’s
Prabu Raja, senior vice president and general manager of the semiconductor products group at Applied Materials, said in a statement that a smartphone chpis has tens of billions of interconnections based on copper wiring, and that takes up a third of a chip’s power. By integrating multiple process technologies in vacuum, Applied Materials can reengineer materials and structures so that consumers can have more capable devices and longer battery life. This unique, integrated solution is designed to accelerate the performance, power and area-cost roadmaps of our customers, Raja said.
The Endura Copper Barrier Seed system is now being used by leading foundry-logic customers worldwide. Additional information about the system and other innovations for logic scaling will be discussed at Applied’s 2021 Logic Master Class being held today.
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